Recent improvements in circuitry of ultra-large scale integration (ULSI) on semiconductor substrates indicate that future generations of semiconductor devices will require even smaller multi-level metallization. The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die as features continue to decrease in size.
Copper and its alloys have become the metals of choice for sub-micron interconnect technology because copper has a lower resistivity than aluminum, a higher current carrying capacity, and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Electroplating is one process being used to fill high aspect ratio features on substrates. Electroplating processes typically require a thin, electrically conductive seed layer to be deposited on the substrate. Electroplating is accomplished by applying an electrical current to the seed layer and exposing the substrate to an electrolytic solution containing metal ions that plate over the seed layer.
Electroless deposition is another process used to deposit conductive materials. Although electroless deposition techniques have been widely used to deposit conductive metals over non-conductive printed circuit boards, electroless deposition techniques have not been extensively used for forming interconnects in VLSI and ULSI semiconductors. Electroless deposition involves an auto catalyzed chemical deposition process that does not require an applied current for a plating reaction to occur. Electroless deposition typically involves exposing a substrate to a solution by immersing the substrate in a bath or by spraying the solution over the substrate.
However, copper readily forms copper oxide when exposed to atmospheric conditions or environments outside of processing equipment and requires a passivation layer to prevent metal oxide formation. Metal oxides can result in an increase the resistance of metal layers, become a source of particle problems, and reduce the reliability of the overall circuit.
Additionally, metal oxides may also detrimentally affect subsequent processing. In one example, oxides may interfere with electroless deposition techniques. Electroless deposition techniques require a surface capable of electron transfer for nucleation, i.e., catalyzing, of a conductive material over that surface, and oxidized surfaces, for example on copper seed layers and metal barrier layers, cannot sufficiently participate in electron transfer for effective electroless deposition.
One solution is to deposit a passivation layer or encapsulation layer on the metal layer to prevent metal oxide formation. Cobalt (CO) and cobalt alloys have been observed as suitable materials for passivating copper. Cobalt may also be deposited by electroless deposition techniques on copper. However, copper does not satisfactorily catalyze or initiate deposition of materials from electroless solutions.
Another solution is to initiate deposition from an electroless solution by contacting the copper substrate with a ferrous material that initiates deposition though a galvanic reaction. However, the process requires a continuous conductive surface over the substrate surface that may not be possible with some passivation applications.
Still another solution is to activate the copper surface by depositing a catalytic material on the copper surface. However, deposition of the catalytic material may require multiple steps or use catalytic colloid compounds. Catalytic colloid compounds may adhere to dielectric materials and result in undesired, excessive, and non-selective deposition of the passivation material on the substrate surface. Non-selective deposition of passivation material may lead to surface contamination, unwanted diffusion of conductive materials into dielectric materials, and even device failure from short circuits and other device irregularities.
Thus, a need still remains for an electroless plating system to provide improved stability and small isolated feature deposition. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.